Science, Technology — June 22, 2022 at 12:36 am

Quantum Computers and CMOS Semiconductors: A Review and Future Predictions

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Well-understood materials will likely play a key role in the quantum era.

With the advent of quantum computing, the need for peripheral fault-tolerant logic control circuitry has reached new heights. In classical computation, the unit of information is a “1” or “0”. In quantum computers, the unit of information is a qubit which can be characterized as a “0”, “1”, or a superposition of both values (known as a “superimposed state”).

The control circuitry in classical computers is CMOS (semiconductor) based, due to its high-performance and low power dissipation. The “1’s” and “0’s” of a classical computer can be manipulated, stored, and easily read using CMOS chips that operate at room temperature. Most quantum computers today operate at cryogenic temperatures, to ensure that the qubit remains coherent (in a superimposed state) for as long as possible. The coherence times are typically very short (nanoseconds to milliseconds) in a quantum computer, prompting the need for control circuitry that can perform high-speed, fault-tolerant operations. This requirement could be met by conventional CMOS control circuitry if it could be operated at cryogenic temperatures.

The first attempt to characterize semiconductor materials at cryogenic temperatures was made by A.K. Jonscher in his 1964 Proceedings of the IEEE publication, entitled “Semiconductors at Cryogenic Temperatures” [1]. His two basic conclusions were: 1) semiconductor devices have no major cryogenic application at that point in time due to “no real technological justification for going on a large scale to these extreme temperatures”, and 2) “the properties of semiconductor materials at cryogenic temperatures are so strikingly different from the familiar properties at higher temperatures, that it is reasonable to expect many more device applications to emerge as a result of continued research and development effort in this direction”. A few years later, IBM became interested in low-temperature semiconductor device operation [2-3] and concluded that MOSFET semiconductor devices show improved performance at cryogenic temperatures. With the advantages of low-temperature operation, scaling-down the cooling apparatus is still an obstacle in using semiconductor-based control circuitry.
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Enter quantum mechanics. In 1959, Richard Feynman challenged the scientific community to employ quantum mechanics in the design of information processing systems. He envisioned new information systems and functions that involved quantized energy levels, and/or the interactions of quantized “spins” (angular momentum of quantum particles). His vision was realized in the 1980s, when it was demonstrated that quantum mechanical, energy-based equations could represent a universal Turing (computational) machine [4]. In 1994, it was shown that a quantum computer could factor integer numbers much more quickly than a classical computer (“in polynomial time”) [5]. This discovery was the catalyst that fostered continued interest in building quantum computing systems. That interest continues today at numerous commercial, research and academic organizations.

Even with the strong interest in building quantum computers, the fact remains that successful operation of this type of computer currently requires a cryogenic temperature environment. Quantum logic control circuitry will also need to operate at these cryogenic temperatures to function effectively in this environment. Thus, we have seen a resurgence of interest in the cryogenic temperature performance of CMOS-based circuitry.

Quantum computers do not require state-of-the-art CMOS circuitry, but CMOS devices operate differently at cryogenic and room temperatures. CMOS transistor performance (and the associated I-V performance) has recently been measured on 40 nm and 160 nm bulk CMOS devices, at both room temperature and at 4.2 degrees Kelvin (see Figure 1). Drive current increases at cryogenic temperatures due to an increase of the mobility in silicon at these temperature. Unfortunately, other effects such as substrate freeze-out can limit the increase in drive current at these low temperatures.

Fig. 1. Measured I-V characteristics of nMOS transistors fabricated in 160nm (left) and 40nm (right) CMOS. Room temperature operation is shown in the dotted curves, liquid helium operation is shown in the solid curves, and a Spice-compatible model fitted to experimental data is shown in the dashed lines. (Taken from [6])
Fig. 1. Measured I-V characteristics of nMOS transistors fabricated in 160nm (left) and 40nm (right) CMOS. Room temperature operation is shown in the dotted curves, liquid helium operation is shown in the solid curves, and a Spice-compatible model fitted to experimental data is shown in the dashed lines. (Taken from [6])
Control circuitry for quantum computers is currently being operated at room temperature. As mentioned earlier, this can be a problem due to the sensitivity of reading the “state” of qubits at higher temperatures. This challenge can be partially alleviated by operating the CMOS circuitry at or near cryogenic temperatures, in the same cryogenic freezers as the quantum computer. This integration can serve to reduce latency and increase overall system scalability. Despite some second order issues, CMOS transistors at low temperatures can perform various functions needed to work with a quantum computer. These functions include the ability to perform as I/V converters, low-pass filters, and A/D and D/A converters (see Figure 2).

Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])
Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])
To achieve the desired performance of a fault-tolerant quantum computer system, a new generation of deep-submicron CMOS circuits will be required that operate at deep-cryogenic temperatures [6]. Extrapolating this idea to its logical conclusion, one ends up with a quantum integrated circuit (QIC) where the array of qubits is integrated on the same chip as the CMOS electronics required to read the state of the qubits. This integration would clearly be the ultimate goal in achieving scalable, reliable, and high performing quantum computing.

In more futuristic applications, optical communications to and from the qubit may also be necessary. In this case, integrated CMOS circuits will also need to include micro- and nano-optical structures, such as light-guides and interferometers. These types of optical functions have been successfully demonstrated on room-temperature CMOS devices. Demonstrating this level of optical communications functionality at cryogenic temperatures may also be desirable in future quantum computing applications.

References
1.) A. K. Jonscher, “Semiconductors at Cryogenic Temperatures”, Proceedings of the IEEE, 1964.
2.) R. W. Keyes, et al., “The Role of Low Temperatures in the Operation of Logic Circuitry,” Proc. IEEE, vol. 58, pp. 1914-1932, 1970.
3.) F. H. Gaensslen, et al., “Very Small MOSFET’s for Low Temperature operation,” IEEE Trans. Electron Devices, vol. ED-24, pp. 218-229, 1877.
4.) P. Benioff, “The Computer as a Physical System: A Microscopic Quantum Mechanical Hamiltonian Model of Computers as Represented by Turing Machines,” J. Stat. Phys., vol. 22, no. 5, pp. 563-591, 1980.
5.) P. Shor, “Algorithms for Quantum Computations: Discrete Log and Factoring,” Proc. 35th Annu. Symp. Found. Comput. Sci., Los Alamitos, CA, 1994, pp. 124-134.
6.) E. Charbon, et al., “Cryo-CMOS for Quantum Computing,” 2016 IEDM, pp. 343-346.

Author

  • Michael Hargrove is a a semiconductor process and integration engineer at Coventor, a Lam Research Company. He has worked in the semiconductor technology development business for more than 30 years. He began his career at IBM, where he worked on advanced CMOS technology development. He then spent five years at Epson Research and Development, working on high-speed/high-frequency device design and characterization. He later joined AMD, where he worked on high-k/metal gate technology. Hargrove subsequently transitioned to GlobalFoundries Research and Development in Albany, NY. At Coventor his focus is 3D semiconductor process modeling. Hargrove received his Ph.D. from the Thayer School of Engineering at Dartmouth College, in Hanover, N.H.

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